Static random access memories (SRAMs) are often used in the portion of a processing systems where speed is very important such as a cache. Most systems have a system clock to which all accesses are timed. There are various memories which can function using a system clock. Another clock which some systems have is an address latch enable signal ALE. In such a system, one logic state of signal ALE indicates that the external addresses are valid and the other state indicates that the addresses are invalid. There can thus be considered the valid state and the invalid state. An edge of a signal is the time at which the signal switches logic states so there are two edges per cycle. The edge which switches between the valid state and the invalid state is the edge at which address signals are to be latched because that is the indication that the address signals can become invalid. This can be considered the latching edge of signal ALE. So long as signal ALE is valid, the memory is intended to be responsive to the address signals. There are set-up and hold-time specifications for the address signals with respect to the latching edge of signal ALE. The set-up time is the time that the address signals must be valid prior to the latching edge of signal ALE in order for those address signals to be the ones that are responded to. The hold time is the time that the address signals must be maintained valid after the latching edge of signal ALE. The total of the set-up and hold times is desirably low. The total of the set-up and hold times is typically about 25% of the access time for a high speed SRAM. Generally, it is also desirable for the set-up and hold times to be about the same although there are some situations in which the hold time is zero at the cost of increasing the set-up time.
In such a system in which signal ALE is used and SRAMs are used, a typical approach is to use a conventional high speed SRAM and additionally use a latch for the addresses. The latch itself adds about 25% to the access time. For example, for a memory with an access time of about 23 nanoseconds, the latch adds about 6 nanoseconds of delay. Such a system is shown in FIG. 1 in which there is an integrated circuit SRAM 10 and a separate latch 11. Latch 11 receives the address signals from some address bus and latches them in response to the latching edge of signal ALE. While signal ALE is valid, latch 11 outputs the address signals at the logic state at which they are received. While signal ALE is invalid, latch 11 outputs the address signals at the logic states which were present at the time of the latching edge of signal ALE. The output of latch 11 will change again only if signal ALE switches to the valid state at which time latch 11 will output the address signals at the same states as that received. Memory 10 is a memory of the type which uses address transition detection (ATD). Memory 10 comprises an input buffer 12 for receiving a single address signal, an internal buffer 13, an ATD and summation circuit 14 for providing an equalization pulse EQ, a decoder 15, an array 16, and an equalization and precharge circuit 17 for receiving pulse EQ. Memory 10 also further comprises elements not shown such as an input buffer and internal buffer for each address signal. Also, ATD and summation circuit 14 may provide additional signals and may be used for purposes other than equalization and precharge.
Input buffer 12 detects the logic state of the received address signal and provides an output which is at full power supply levels. Internal buffer 13 provides the address signals to decoder 15 and fast and slow address signals to ATD and summation circuit 14 for detection of an address transition. ATD and summation circuit 14 uses slow and fast address signals to determine if an individual address has changed and, if one or more of individual address signals has changed state, generates equalization pulse EQ. Equalization and precharge circuit 17 equalizes and precharges the bit line pairs of array 16 in response to pulse EQ. Decoder 15 selects a predetermined number of cells, according to the part type such as .times.11, .times.4, .times.8, etc., within array 16 for reading or writing. A particularly effective input buffer for use as input buffer 12 and internal buffer 13 is described in U.S. Pat. No. 4,807,198, Flannagan et al., which issued Feb. 21, 1989. The buffer described therein is particularly useful as an input buffer for an ATD memory by being effective in providing both desirable hysteresis and D.C. margin.
One advantage of having a memory with a latch such as 11 included therein is that of reducing the part count to achieve the desired function. The reduced part count would reduce the amount of board space required. The board would also then not have to have separate routing for the latched addresses. Of course addresses would still need to come to the memory but the bus which carried the unlatched addresses might also be close by anyway. There is also the potential for reducing the increase in access time due to the extra latch. An internal latch would certainly be expected to operate faster than 6 nanoseconds.